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Integrated Circuit Systems, Inc.
ICS9248-103
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9248-103 is the single chip clock solution for Notebook designs using the 440BX or the VIA Apollo Pro 133 style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-103 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Features
Up to 137MHz frequency support Spread Spectrum for EMI control Serial I2C interface for Power Management, Frequency Select, Spread Spectrum Provides the following system clocks - 4-CPUs @ 2.5/3.3V, up to 137MHz (including CPUCLK_F) - 9-SDRAMs @3.3V, up to 137MHz (including SDRAM_F) - 8-PCI @3.3V, CPU/2 or CPU/3 (including 3 free running PCICLK_Fs) - 1-24/48MHz @3.3V - 1-48MHz @3.3V fixed - 2-REF @3.3V, 14.318MHz. Efficient Power management scheme through PCI and STOP CLOCKS Spread Spectrum .25%, & 0 to -0.5% down spread
Block Diagram
Pin Configuration
Power Groups
VDDLCPU, GNDLCPU = CPUCLK [2:0], CPUCLK_F VDDSDR, GNDSDR = SDRAMCLKS [7:0], SDRAM_F VDDPCI, GNDPCI = PCICLKS [6:0], PCICLK_F VDD48, GND48 = 48MHz, 24MHz VDDREF, GNDREF = REF, X1, X2 VDDCOR = PLL CORE
9248-103 Rev C 10/14/99
48-Pin SSOP
* Internal Pull-up Resistor of 120K to VDD
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-103
Pin Descriptions
PIN NUMBER 1 2 20 3, 9, 16, 33, 40, 44 4 5 6,14 7 PCICLK_F0 FS3 8
1,2
P I N NA M E VDDREF REF0 PCI_STOP# GND X1 X2 VDDPCI C PU2.5_3.3#1,2
TYPE PWR OUT IN PWR IN OUT PWR IN OUT IN OUT
1,2
DESCRIPTION Ref, XTAL power supply, nominal 3.3V 14.318 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads Halts PCICLK [4:0]clocks at logic 0 level, when input low (In mobile mode, MODE=0) Ground Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Supply for PCICLK_F and PCICLK [6:0], nominal 3.3V Indicates whether VDDLC PU is 2.5 or 3.3V. High=2.5V C PU, LO W=3.3V C PU. Latched Input. Free running PCI clock not affected by PCI_STOP# for power management. Frequency select pin. Latched Input. Free running PCI clock not affected by PCI_STOP# for power management. Selects either 24 or 48MHz when Low = 48MHz Free running PCI clock not affected by PCI_STOP# for power management. PCI clock output Synchronous to CPU clocks with 1-4ns skew (CPU early) PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early) Input to Fanout Buffers for SDRAM outputs. Power pin for the PLL core. 3.3V Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled a n d t h e V C O a n d t h e c r y s t a l a r e s t o p p e d . T h e l a t e n cy o f t h e power down will not be greater than 4ms. Ground pin for 24 & 48MHz output buffers & fixed PLL core. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). Supply for SDRAM [7:0] and CPU PLL Core, nominal 3.3V. Data input for I2C serial input, 5V tolerant input Clock input of I2C input, 5V tolerant input 24MHz or 48MHz output clock selectable by pin 10 Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input Power for 24 & 48MHz output buffers and fixed PLL core. Free running SDRAM clock output. Not affected by CPU_STOP# This asynchronous input halts CPUCLK & SDRAM (0:7) at logic "0" level when driven low. CPU clock outputs, powered by VDDLCPU Free running CPU clock. Not affected by the CPU_STOP# Supply for CPU clocks 2.5V 14.318 MHz reference clock. Frequency select pin. Latched Input
PCICLK_F1 SEL24_48#MHz
IN OUT O UT OUT IN PWR IN PWR OUT PWR IN IN OUT IN OUT IN PWR OUT IN OUT OUT PWR OUT IN
10 11 18, 17, 13, 12 15 19 21 22 28, 29, 31, 32, 34, 35, 37, 38 30, 36 23 24 25 26 27 39 41 42, 43, 45 46 47 48
PCICLK_F2 PCICLK1 PCICLK [5:2] BUFFER IN VDDCOR PD#1 GND48 SDRAM [7:0] VDDSDR SDATA SCLK 24_48MHz FS1
1, 2
48MHz FS01, 2 VDD48 SDRAM_F CLK_STOP# CPUCLK [2:0] CPUCLK_F VDDLCPU REF1 FS21, 2
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
2
ICS9248-103
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
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ICS9248-103
Functionality
VDD = 3.3V5%, VDDL = 2.5V5% or 3.35%, TA=0 to 70C Crystal (X1, X2) = 14.31818MHz
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 124.00 120.00 114.99 109.99 105.00 83.31 137.00 75.00 100.00 95.00 83.31 133.33 90.00 96.22 66.82 91.5 PCI (MHz) 41.33 40.00 38.33 36.66 35.00 41.65 34.25 37.50 33.33 31.67 27.77 33.33 30.00 32.07 33.41 30.5
Serial Configuration Command Bitmap
Bit Bit 7
Byte0: Functionality and Frequency Select Register (default = 0)
Description 0 - 0.25% Spread Spectrum Modulation, Center Spread 1 - 0 to -0.5% Down Spread CPUCLK PCICLK Bit [2, 6:4] (MHz) (MHz) 0000 124.00 41.33 0001 120.00 40.00 0010 114.99 38.33 0011 109.99 36.66 0100 105.00 35.00 0101 83.31 41.65 0110 137.00 34.25 0111 75.00 37.50 1000 100.00 33.33 1001 95.00 31.67 1010 83.31 27.77 1011 133.33 33.33 1100 90.00 30.00 1101 96.22 32.07 1110 66.82 33.41 1111 91.5 30.5 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit [2, 6:4] 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1- Tristate all outputs PWD 1
Bit [2, 6:4]
Note1
Bit 3 Bit 1 Bit 0
0 1 0
Note 1, Default at Power-up will be for latched logic inputs to define frequency. Bit [2, 6:4] are default to 0010. Note 2, PWD = Power-Up Default Note 3, When disabling spread spectrum bit7 needs to be set to 0 to maintain nominal frequency.
4
ICS9248-103
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 46 39 42 43 45 PWD 1 1 1 1 1 1 1 1 Description (Reserved) CPUCLK_F (Act/Inact) (Reserved) (Reserved) SDRAM_F (Act/Inact) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 7 18 17 13 12 11 10 8 PWD 1 1 1 1 1 1 1 1 Description PCICLK_F0 (Act/Inact) PCICLK4(Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0 (Act/Inact) PCICLK_F1 (Act/Inact) PCICLK_F2 (Act/Inact)
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 29 31 32 PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
5
ICS9248-103
Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # PWD 1 1 1 1 X 1 X 1 Description (Reserved) (Reserved) (SEL24_48)# (Reserved) Latched FS1# (Reserved) Latched FS3# (Reserved)
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 34 35 37 38 26 25 48 2 PWD 1 1 1 1 1 1 1 1 Description SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact) 48MHz (Act/Inact) 24MHz (Act/Inact) REF1 (Act/Inact) REF0 (Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
6
ICS9248-103
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-103. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL CPUCLK PCICLK [6:0] CLK_STOP# PCI_STOP# (High)
SDRAM [7:0] CPUCLK [2:0] CPUCLK _F SDRAM_F
Notes: 1. All timing is referenced to the internal CPU clock. 2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-103. 3. IOAPIC output is Stopped Glitch Free by CPUSTOP# going low. 4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-103 CLK_STOP# signal. SDRAM [7:0] are controlled as shown. 5. All other clocks continue to run undisturbed.
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ICS9248-103
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 4 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CLK_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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ICS9248-103
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-103. It is used to turn off the PCICLK [4:0] clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-103 internally. The minimum that the PCICLK [4:0] clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK [4:0] clocks. PCICLK [4:0] clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK [4:0] clock on latency cycles are only three rising PCICLK clocks off latency is one PCICLK clock.
CPUCLK (Internal)
PCICLK_F (Internal) PCICLK_F (Free-running) CLK_STOP#
PCI_STOP#
PCICLK [6:0]
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. CLK_STOP# is shown in a high (true) state.
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ICS9248-103
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248103 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
Fig. 1
10
ICS9248-103
Fig. 2a
Fig. 2b
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ICS9248-103
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND 0.5 V to VDD +0.5 V 0C to +70C 115C 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characte ristics - Input/Supply/Com m on Output Param ete rs
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unles s otherwis e s tated) PA RA M ETER Input High Voltage Input Low Voltage Operating Supply Current Powerdown Current Input Frequency Input Capacitance Clk Stabilization Skew
1 1 1 1
SYM BOL VIH VIL IDD3.3 OP IDDP D Fi CIN CINX TSTAB tCP U -P CI1
CONDITIONS
M IN 2 VSS-0.3
TYP
C L = 0 pF; Select @ 66M Hz C L = 0 pF; Select @ 100M Hz C L = 0 pF; Select @ 133M Hz CL = 0 pF; Input address VDD or GND VDD = 3.3 V Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq. VT = 1.5 V 1 12 27
90 120 151 250 14.318 36 2.8
MAX VDD+0.3 0.8 150 170 180 600 16 5 45 5.5 4
UNITS V V mA A MHz pF pF ms ns
Guaranteed by des ign, not 100% tes ted in production.
Ele ctrical Characte ristics - Input/Supply /Com m on Output Param e te rs
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unles s otherwis e s tated) PA RA M ETER Operating SupplyCurrent Powerdown Current Skew
1 1
SYMBOL IDDL2.5 IDDLP D tCP U -P CI2
CONDITIONS CL = 0 pF; Select @ 66.8 M Hz CL = 0 pF; Select @ 100 M Hz CL = 0 pF; Select @ 133 M Hz
CL = 0 pF; Input address VDD or GN D
M IN
TYP 8 11 17 <1 2.4
MAX 15 18 20 10 4
UNITS mA A ns
VT = 1.5 V; VTL = 1.25 V
1
Guaranteed by des ign, not 100% tes ted in production.
12
ICS9248-103
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF PARAMETER SYMBOL IOH = -20 mA Output High Voltage VOH2A Output Low Voltage VOL2A IOL = 12 mA Output High Current IOH2A VOH = 2.0 V VOL = 0.8 V Output Low Current IOL2A Rise Time1 Fall Time1 Duty Cycle
1 1
CONDITIONS
MIN 2.4
22
TYP 2.85 0.31 -45 29 1.5 1.4
MAX UNITS V 0.4 V -27 mA mA 2 2 55 175 250 ns ns % ps ps
tr2A tf2A dt2A tsk2A tjcyc-cyc2A
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 45
Skew window Jitter, Cycle-to-cycle1
1
80 200
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 20 pF PARAMETER SYMBOL Output High Voltage VOH2B IOH = -12 mA Output Low Voltage VOL2B IOL = 12 mA Output High Current IOH2B VOH = 1.7 V Output Low Current IOL2B VOL = 0.7 V Rise Time Fall Time
1
CONDITIONS
MIN 2
22
TYP 2.3 0.31 -39 26 1.3 1.4 47.5 47 70 200
MAX UNITS V 0.4 V -21 mA mA 1.6 1.6 55 52 175 300 ns ns % ps ps
tr2B tf2B dt2B tsk2B tjcyc-cyc2B
VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V, < 133 MHz VT = 1.25 V, >= 133 MHz VT = 1.25 V VT = 1.25 V 45 42
1
Duty Cycle1 Skew window1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
13
ICS9248-103
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1 IOH = -18 mA Output Low Voltage VOL1 IOL = 9.4 mA Output High Current IOH1 VOH = 2.0 V Output Low Current IOL1 VOL = 0.8 V Rise Time Fall Time
1
MIN 2.4
38
TYP 3 0.2 -62 43 1.5 1.5
MAX UNITS V 0.4 V -33 mA mA 2 2 55 500 150 250 ns ns % ps ps ps
tr1 tf1 dt1
1 1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V -250 45
1 1
Duty Cycle
50 180 15 75
Skew window
tsk1 tj1s1 tjabs1
Jitter, One Sigma Jitter, Absolute1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle
1 1 1
SYMBOL VOH3 VOL3 IOH3 IOL3 Tr3 Tf3 Dt3 Tsk3 Tsk3
CONDITIONS IOH = -28 mA IOL = 19 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
32
TYP 3 0.3 -69 42 1 1.3 50 185 4
MAX UNITS V 0.4 V -46 mA mA 1.3 ns 2 55 250 5 ns % ps ns
45
Skew window
Propagation Time (Buffer In to output)
1
Guaranteed by design, not 100% tested in production.
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ICS9248-103
Electrical Characteristics - 24,48MHz, REF(0:1)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH5 IOH = -14 mA IOL = 6 mA Output Low Voltage VOL5 VOH = 2.0 V Output High Current IOH5 VOL = 0.8 V Output Low Current IOL5 Rise Time Fall Time
1
MIN 2.4
16
TYP 2.6 0.22 -32 22 2 2
MAX UNITS V 0.4 V -20 mA mA 4 4 55 250 600 ns ns % ps ps
tr5 tf5 dt5
1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V -600 45
1 1
Duty Cycle
1 150
Jitter, One Sigma Jitter, Absolute1
1
tj1s5 tjabs5
Guaranteed by design, not 100% tested in production.
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ICS9248-103
SYMBOL A A1 A2 B C D E e H h L N
X
COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100
VARIATIONS AC MIN. .620
D NOM. .625
N MAX. .630 48
SSOP Package
Ordering Information
ICS9248yF-103
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
16

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